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OR Gates#

Definition: OR Gate

An \(n\)-input OR gate is a logic gate which computes a disjunction \(\mathop{\mathrm{OR}}: \{0,1\}^n \to \{0, 1\}\).

Notation

The following symbols are used for OR gates:

OR Gate Symbol

Here is the truth table for this gate when \(n = 2\):

\(A\) \(B\) \(\mathop{\operatorname{OR}}(A, B)\)
\(0\) \(0\) \(0\)
\(0\) \(1\) \(1\)
\(1\) \(0\) \(1\)
\(1\) \(1\) \(1\)

CMOS Implementation#

Algorithm: OR Gate via CMOS

An OR gate with \(n\) inputs is implemented via CMOS as follows:

  1. Create a top layer of \(n\) PMOS transistors in series.
  • Connect the source of the top PMOS to the supply \(V_{\text{DD}}\).
  • Connect the gate of the \(i\)-th PMOS to the \(i\)-th input.
  1. Create a bottom layer of \(n\) NMOS transistors in parallel.
  1. Connect the drain of the bottom PMOS to the drain of each NMOS and drive this connection into the input of an inverter.