NAND Gates#
Definition: NAND Gate
A NAND gate is a logic gate which computes the negation of a conjunction:
\[\mathop{\operatorname{NOT}} \circ \mathop{\operatorname{AND}}\]
Notation
The following symbols are used for NAND gates:
Here is the truth table for this gate when \(n = 2\):
| \(A\) | \(B\) | \(\mathop{\operatorname{NAND}}(A, B)\) |
|---|---|---|
| \(0\) | \(0\) | \(1\) |
| \(0\) | \(1\) | \(1\) |
| \(1\) | \(0\) | \(1\) |
| \(1\) | \(1\) | \(0\) |
CMOS Implementation#
A NAND gate can be implemented using CMOS in the following way:
Algorithm: NAND Gate via CMOS
A NAND gate with \(n\) inputs is implemented via CMOS as follows:
- Create a top layer of \(n\) PMOS transistors in parallel.
- Connect the source of each PMOS to the supply \(V_{\text{DD}}\).
- Connect the gate of the \(i\)-th PMOS to the \(i\)-th input.
- Create a bottom layer of \(n\) NMOS transistors in series.
- Connect the source of the bottom NMOS to ground.
- Connect the gate of the \(i\)-th NMOS to the \(i\)-th input.
- Connect the drains of all PMOS to the drain of the top NMOS and drive this connection as the output.
Example: 2-Input NAND
