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AND Gates#

Definition: AND Gate

An \(n\)-input AND gate is a logic gate which computes a conjunction \(\mathop{\mathrm{AND}}: \{0,1\}^n \to \{0, 1\}\).

Notation

The following symbols are used for AND gates:

AND Gate Symbol

Here is the truth table for this gate when \(n = 2\):

\(A\) \(B\) \(\mathop{\operatorname{AND}}(A, B)\)
\(0\) \(0\) \(0\)
\(0\) \(1\) \(0\)
\(1\) \(0\) \(0\)
\(1\) \(1\) \(1\)

CMOS Implementation#

Algorithm: AND Gate via CMOS

An AND gate with \(n\) inputs is implemented via CMOS as follows:

  1. Create a top layer of \(n\) PMOS transistors in parallel.
  • Connect the source of each PMOS to the supply \(V_{\text{DD}}\).
  • Connect the gate of the \(i\)-th PMOS to the \(i\)-th input.
  1. Create a bottom layer of \(n\) NMOS transistors in series.
  1. Connect the drains of all PMOS to the drain of the top NMOS and drive this connection into the input of an inverter.