Circuit Timing#

Nothing in the physical world happens instantaneously and this applies to digital circuits as well. There are always delays involved between the changes in the inputs of a digital circuit and the corresponding changes in its outputs. Moreover, a signal itself cannot instantaneously switch between $0$ and $1$ or vice-versa. This transition also takes time.

These delays must be taken into account to ensure that a digital circuit will function properly.

Transition Times#

The transition of a signal from a LOW to a HIGH state or vice-versa is very fast, but still gradual and takes time.

Definition: Transition Time

The time it takes for a signal to change from one state to another is known as transition time.

In practice, it matters whether the signal goes from a LOW to a HIGH state or from a HIGH to a LOW state and so we usually have two different transition times for each signal.

Definition: Rise Time

The rise time is the time it takes for a signal to go from a LOW state, to a HIGH state.

Note

Most commonly, rise time is measured as the time it takes for the signal to go from 10% to 90% of the final voltage.

Signal Rise Time

Definition: Fall Time

The fall time is the time it takes for a signal to go from a HIGH state to a LOW state.

Note

Most commonly, rise time is measured as the time it takes for the signal to go from 90% to 10% of the final voltage.

Signal Fall Time

Contamination and Propagation#

Digital circuits are really fast but still operate at a finite speed, which introduces delays. As the complexity of a circuit grow, the paths between its inputs and outputs get more complicated and the delays from their components begin to add up. This means that it takes more time for a change in the inputs to be reflected in the outputs.

Definition: Contamination Delay

Let $C$ be a digital circuit with $m$ inputs $I_1, \dotsc, I_m$ and $n$ outputs $O_1, \dotsc, O_n$.

The ****

Definition: Propagation Delay

Let $C$ be a digital circuit with $m$ inputs $I_1, \dotsc, I_m$ and $n$ outputs $O_1, \dotsc, O_n$.

The high-to-low propagation delay between $I_j$ and $O_k$ is the time elapsed between $I_j$ transitioning $50 \%$ and the output $O_k$ transitioning $50 \%$.

Notation

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Definition: Contamination Delay

The contamination delay of a digital circuit is the minimum time it takes for an output to begin transitioning into a stable after a change in the input.

Definition: Propagation Delay

The propagation delay of a digital circuit is the maximum time it takes for an output to finish transitioning into a stable state after a change in the input.

In practice, contamination delays and propagation delays are measured starting when the input transition is at $50 \%$ until the output transition is also at $50 \%$.

Contamination and Propagation

We also usually have two different contamination delays and two different propagation delays depending on whether the output is switching from LOW to HIGH or vice-versa. Moreover, in reality each path in a digital circuit has its own LOW-to-HIGH and HIGH-to-LOW contamination delay and its own LOW-to-HIGH and HIGH-to-LOW propagation delays. The contamination delays and propagation delays of the entire circuit are then the minimum and maximum of these delays, respectively.

Notation

We denote the contamination delays by $t_{\text{cLH}}$ and $t_{\text{cHL}}$ and the propagation delays by $t_{\text{pLH}}$ and $t_{\text{pHL}}$.

Essentially, the contamination delay of a digital circuit is the minimum possible delay before any of its outputs begins changing. We have to wait for contamination delay to see any change in the output. Otherwise we would just be reading its old state, which is not particularly useful.

By contrast, the propagation delay of a digital circuit is the maximum possible delay before all its outputs have settled into a stable state. Once the propagation delay has passed, we are guaranteed to have a meaningful state for the outputs, but not before that.

Trying to read off the output of a digital circuit in the time interval between its contamination delay and propagation delay can therefore result in an invalid or spurious state for the output. This is why the propagation delayultimately limits the maximum speed at which the digital circuit can operate: we must wait for the propagation delay to pass, lest we run the risk of encountering a bad output state.

Synchronization#

Definition: Synchronous Circuit

A digital circuit is synchronous if it is made up of edge triggered devices whose active period is tied to a common signal.

Usually, this common signal is a clock signal with a specific period $T_{\text{clk}}$.

To operate a synchronous circuit correctly, the timing parameters of its components must be taken into account.

Important: Setup Constraint

The timing parameters of a synchronous circuit are subject to the setup constraint

\[ T_{\text{clk}} \ge t_{\text{setup}} + t_{\text{logic,max}} + t_{\text{c2q}}, \]

where:

$T_{\text{clk}}$ is the period of the common clock signal;
$t_{\text{logic,max}}$ is the propagation delay of the slowest combinational path between two components triggered by the clock signal;
$t_{\text{setup}}$ is the setup time of the sourceof this path;
$t_{\text{c2q}}$ is the propagation delay of the destination of this path.

Important: Hold Constraint

The timing parameters of a synchronous circuit are subject to the hold constraint

\[ t_{\text{hold}} \le t_{\text{logic,min}} + t_{c2q}, \]

where:

$t_{\text{logic,min}}$ is the propagation delay of the fastest combinational path between two components triggered by the clock signal;
$t_{\text{hold}}$ is the hold time of the source of this path;
$t_{\text{c2q}}$ is the propagation delay of the destination of this path.