CMOS#
Complementary MOS (CMOS) refers to the use of both PMOS and NMOS to build digital circuits.
There are many reasons why CMOS dominates digital circuits in today's world.
Technical reasons:
- Low power dissipation: It consumes very little power compared to other technologies.
- High noise immunity: It is largely insensitive to electrical interference or disturbances. Moreover, noise is reduced as a signal propagates further through a circuit.
- Clean logic levels: It produces distinct and reliable high/low voltage signals.
- Single supply voltage: It only requires one power source to operate.
- Cascadability: Components can be easily connected in series.
Economic reasons:
- Simple design: Circuits are relatively easy to design using CMOS.
- Mature manufacturing: The production process has been well-understood and mastered.
- High integration: It allows for a very high density of transistors, making it suitable for complex integrated circuits (chips).
CMOS Design#
Every Boolean function \(f: \{0,1\}^n \to \{0,1\}\) can be implemented via CMOS.
Algorithm: CMOS Design from Boolean Expression
We are given an arbitrary Boolean expression of a Boolean function \(f: \{0,1\}^n \to \{0,1\}\) and want to implement \(f\) via CMOS:
- Create a pull-up network (PUN) from PMOS transistors by traversing the expression recursively.
- Each conjunction (AND) in the expression is physically implemented by arranging the corresponding sub-networks in parallel.
- Each disjunction (OR) in the expression is physically implemented by arranging the corresponding sub-networks in series.
- The gate of each PMOS is connected to exactly one literal.
- The sources of the top-most PMOS transistors are connected to the supply \(V_{\text{DD}}\).
- Create a pull-down network (PDN) from NMOS transistors by traversing the expression recursively.
- Each conjunction (AND) in the expression is physically implemented by arranging the corresponding sub-networks in series.
- Each disjunction (OR) in the expression is physically implemented by arranging the corresponding sub-networks in parallel.
- The gate of each NMOS is connected to exactly one literal.
- The sources of the bottom-most NMOS transistors are connected to ground.
- Connect the two networks by connecting the drains of the bottom-most PMOS transistors to the drains of the top-most NMOS transistors and drives this common connection into an inverter.
- The output of this inverter is \(f\).