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The MMIX Processor#

The MMIX architecture features a simple 64-bit processor comprised of the following:
- 256 registers which are general-purpose registers and are labelled $0, $1, ..., $255. Each is 64 bits wide.
- 32 registers which are special registers and are labelled rA, rB, rC, ..., rZ, rBB, rTT, rWW, rXX, rYY, rZZ. Each is 64 bits wide.
- an arithmetic-logic unit (ALU) with two 64-bit inputs and one 64-bit output.

The two inputs of the ALU are connected to all general-purpose registers via a multiplexer and its output is also connected to all general-purpose registers via a demultiplexer.

Data Organization#

The MMIX architecture logically groups bits in the following way:
- 1 byte = 8 bits;
- 1 wyde = 2 bytes = 16 bits;
- 1 tetra = 2 wydes = 4 bytes = 32 bits;
- 1 octa = 2 tetras = 4 wydes = 8 bytes = 64 bits;

The MMIX processor is big-endian, i.e. it always addresses the most significant byte, while the rest of the bytes are stored at the subsequent, higher addresses.

General-Purpose Registers#

The general-purpose registers are connected via 64-bit bus to a storage device which contains \(2^{64}\) cells, each 8-bit in size.

For the most part, they can be used for any purpose. However, they are divided into three groups, whose boundaries are determined by the
- The local registers begin (inclusively) at $0 and end (exclusively) with the general-purpose register whose number is stored in the rL special register.
- The marginal registers begin (inclusively) with the general-purpose register whose number is stored in the rL special register and end (exclusively) with the general-purpose register whose number is stored in the rG special register.
- The global registers begin (inclusively) with the general-purpose register whose number is stored in the rG special register and end (inclusively) at $255.

MMIX General-Purpose Registers

The global register $0 contains argc, $1 contains argv and $255 contains the address of main.

Special Registers#

The values of the special registers are strictly determined by the state of the processor and the operations it is executing.